Overview

• All-in-one Ethernet Controller : Hardware TCP/IP, MAC & PHY
• Fully hardwired network protocol 
• Direct & Indirect Bus and SPI for Host Interface
• Stable Data Communication

The W5100 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier Internet connection for embedded systems.

W5100 suits users in need of stable Internet connectivity best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY. Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE, …, which has been proven through various applications over many years. W5100 uses a 16ytes internal buffer as its data communication memory.

By using W5100, users can implement the Ethernet application they need by using a simple socket program instead of handling a complex Ethernet Controller.

It is possible to use 4 independent hardware sockets simultaneously. BUS (Direct  & Indirect) & SPI (Serial Peripheral Interface) are provided for easy integration with the external MCU.

Key Features

• Hardwired TCP/IP protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
• Un-attackable hardware network engine for preventing network attacks such as flooding, spoofing, injection
• Host Interface : Direct/Indirect Bus & Serial Peripheral Interface (SPI MODE 0, 3)
• 4 Independent hardware socket
• Internal 16Kbytes memory for TCP/IP packet processing
• 10BaseT / 100Base TX Ethernet PHY Embedded
• Support Auto-Negotiation (Full & Half Duplex, 10 & 100 Based)
• Support Auto-MDIX
• 3.3V Operation with 5V I/O signal tolerance
• LED outputs (TX, RX, full/half duplex, Collision, link, speed)
• 80LQFP lead-free package (10x10mm)

Download

Datasheet

W5100 Chip Erratasheet v2.6

Limitation Note

W5100 Qualification Report

Application Note

W5100 ioLibrary (Driver) 

W5100 Reference Schematic